Senior IC Layout Engineer— Lead Top-Level Tape-Out, Neuchâtel

A technology-based company in Switzerland is seeking an experienced IC Layout Engineer with over 10 years in Analog/RF design. This role focuses on delivering innovative IC layouts for CMOS projects and requires expertise in Cadence tools. Responsibilities include executing layout tasks, leading verification processes, and driving best practices in ultra-low-power designs. Strong communication skills in English, with knowledge of French or German as an asset, are preferred. Join a team committed to high-quality IC designs and innovations in technology.#J-18808-Ljbffr