Senior FPGA Design Engineer - High-Speed Signal Processing, Lausanne

ViaSat Antenna Systems SA in Lausanne is looking for a skilled Programmable Logic Design Engineer to develop FPGA designs for next-generation terminal products. Candidates should have 10-12 years of experience in FPGA design, particularly with Altera Quartus and Xilinx Vivado, and strong knowledge of System Verilog.The role involves collaborating with teams on high-speed digital signal processing algorithms and managing the design process from requirements to testing and integration. Excellent English proficiency is required.

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